(1) Field of the Invention
The present invention relates to split-gate memory cells used in flash EEPROMs (Electrically Erasable Programmable Read Only Memories), and in particular, to a method of forming a sharp peak of poly to improve erase speed in split-gate flash cell.
(2) Description of the Related Art
The shape and size of different portions of memory cells have different effects on the performance of the memory cells in different ways. Thus, with the one-transistor memory cell, which contains one transistor and one capacitor, many variations of this simple cell have been advanced for the purposes of shrinking the size of the cell and, at the same time, improve its performance. The variations consist of different methods of forming capacitors, with single, double or triple layers of polysilicon, and different materials for the word and bit lines. Another variation which is disclosed in this invention relates to the shape of the edge of the floating gate which significantly affects the erase speed of split-gate flash memory cells.
Memory devices include electrically erasable and electrically programmable read-only memories (EEPROMs) of flash electrically erasable and electrically programmable read-only memories (flash EEPROMs). Many types of memory cells for EEPROMs or flash EEPROMs may have source and drains regions that are aligned to a floating gate or aligned to spacers. When the source and drain regions are aligned to the floating gate, a gate electrode for a select transistor is separate from the control gate electrode of the floating gate transistor. Separate select and control gates increase the size of the memory cell. If the source and drain regions are aligned to a spacer formed after the floating gate is formed, the floating gate typically does not overlie portions of the source and drain regions. Programming and erasing performance is degraded by the offset between the floating gate and source and drain regions.
Most conventional flash-EEPROM cells use a double-polysilicon (poly) structure of which the well known split-gate cell is shown in FIGS. 1g. The forming of the cell is shown in FIGS. 1a-1f which will be described shortly. In the final form of the cell shown in FIG. 1g, a MOS transistor is formed on a semiconductor substrate (10) having a first doped region (11), a second doped region (13), a channel region (15), a gate oxide (20), a floating gate (30), intergate dielectric layer (60) and control gate (70). Substrate (10) and channel region (15) have a first conductivity type, and the first (11) and second (13) doped regions have a second conductivity type that is opposite the first conductivity type.
As seen in FIG. 1g, the first doped region, (11), lies within the substrate. The second doped region, (13), lies within substrate (10) and is spaced apart form the first doped region (11). Channel region (15) lies within substrate (10) and between first (11) and second (13) doped regions. Gate oxide layer (20) overlies substrate (10). Floating gate (30), to which there is no direct electrical connection, and which overlies substrate (10), is separated from substrate (10) by a thin layer of gate oxide (20) while control gate (70), to which there is direct electrical connection, is generally positioned over the floating gate with intergate oxide (60) therebetween.
In the structure shown in FIG. 1g, control gate (70) overlaps the channel region, (17), adjacent to channel (15) under the floating gate, (30). This structure is needed because when the cell is erased, it leaves a positive charge on the floating gate. As a result, the channel under the floating gate becomes inverted. The series MOS transistor (formed by the control gate over the channel region) is needed in order to prevent current flow from control gate to floating gate. The length of the transistor, that is the overlap of the control gate over the channel region (17) determines the cell performance. Furthermore, the shape of the edge (33) and, in particular, that of edge (37) can affect the programming of the cell. It is disclosed in this invention that the shape and size of edge (37) will affect the programming erase speed of the cell substantially. The relatively rounded shape that is found in conventional cells shown in FIG. 1g and which affects the erase speed adversely is the result of the commonly used process which is illustrated in FIGS. 1a-1f.
In FIG. 1a, layer of gate oxide (20) is thermally grown over substrate (10) using conventional methods. Next, a first polysilicon layer (30) is formed followed by the deposition of nitride layer (40). A photoresist layer (50) is then spun over the substrate and then patterned with a floating gate pattern, which in turn, is etched into the nitride layer as shown in FIG. 1b. The photoresist layer, which is no longer needed, is removed. Next, the first polysilicon that is exposed in the pattern openings in the nitride layer is oxidized to form polyoxide (35) as shown in FIG. 1c. Subsequently, the nitride layer is removed leaving the polyoxide as shown in FIG. 1d, where now the polyoxide serves as a hard mask to remove all the first polysilicon portions except those that are covered by the polyoxide. As is well known in the art, this is usually accomplished by main etch followed by over-etch. It is at this etching step that the corner edge (37) is usually rounded off, as seen in FIG. 1e, which is not desirable for achieving fast program erase speed described below. It will be shown later in the embodiments of this invention that by employing a different process step, the sharpness of corner edge (37) can be preserved such that charge transfer (23) between substrate (10) and floating gate (30), and then the charge transfer (63) between the floating gate and control gate, (70), is fast. The Control gate is formed by depositing a second polysilicon layer over intergate layer (60), also known as interpoly, which separates the two polysilicon layers, namely, the floating polygate and the control polygate.
To program the transistor shown in FIG. 1g, which is an enlarged view of FIG. 1f as well as showing the placement of gate, source and drain voltages or Vg, V.sub.s and V.sub.d, respectively, charge is transferred from substrate (10) through gate oxide (20) and is stored on floating gate (30) of the transistor. The amount of charge is set to one of two levels to indicate whether the cell has been programmed "on" of "off." "Reading" of the cell's state is accomplished by applying appropriate voltages to the cell source (11) and drain (13), and to control gate (70), and then sensing the amount of charge on floating gate (30). To erase the contents of the cell, the programming process is reversed, namely, charges are removed from the floating gate by transferring them back to the substrate through the gate oxide.
This programming and erasing of an EEPROM is accomplished electrically and in-circuit by using Fowler-Nordheim tunneling as is well known in prior art. Basically, a sufficiently high voltage is applied to the control gate and drain while the source is grounded to create a flow of electrons in the channel region in the substrate. Some of these electrons gain enough energy to transfer from the substrate to the floating gate through the thin gate oxide layer by means of Fowler-Nordheim tunneling. The tunneling is achieved by raising the voltage level on the control gate to a sufficiently high value of about 12 volts. As the electronic charge builds up on the floating gate, the electric field is reduced, which reduces the electron flow. When, finally, the high voltage is removed, the floating gate remains charged to a value larger than the threshold voltage of a logic high that would turn it on. Thus, even when a logic high is applied to the control gate, the EEPROM remains off. Since tunneling process is reversible, the floating gate can be erased by grounding the control gate and raising the drain voltage, thereby causing the stored charge on the floating gate to flow back to the substrate. Of importance in the tunneling region is the quality and the thinness of the tunneling oxide separating the floating gate from the substrate. Usually a thickness of between about 80 to 120 Angstroms is required to facilitate Fowler-Nordheim tunneling.
Several different methods of forming split-gate flash memory cells are described in prior art. Ahn in U.S. Pat. No. 5,652,161 is concerned about the degradation of the tunnel oxide in a flash EEPROM cell due to the band-to-band tunneling and the secondary hot carrier which are generated by a high electric field formed at the overlap regions between the junction region and the gate electrode when programming and erasure operations are performed by a high voltage to the structure in which the tunneling region is separated from the channel with a thick insulation film. In a separate U.S. Pat. No. 5,614,747, Ahn, et al., disclose a different method for manufacturing a flash EEPROM cell in order to prevent over-erasure of the cell and decrease the cell area by forming a floating gate in the form of a spacer on a side wall of a select gate and by forming a control gate to surround the select gate and the floating gate.
Hong, et al, describe in U.S. Pat. No. 5,422,292 another process for fabricating split-gate flash EEPROM memory where the isolation between the floating gate and the control gate is improved by using a first and second oxide layer so that the problem of leakage does not occur. Jeng, on the other hand, discloses a method of re-crystallizing a floating gate for the purposes of maximizing the coupling between the floating gate and the drain and the portion of the channel regions over which the gate is disposed.
In addition to these prior methods, what is needed is a method for improving the program erase speed of split-gate flash memory cells by shaping the edge of the floating gate as disclosed in the present invention.